Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed dielectric layers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by inter-wiring spacings. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region or a gate/metal region. Conductive lines are formed in trenches, which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor chips comprising eight or more levels of metallization are becoming more prevalent as device geometries have shrunk to half-micron levels and to a tenth of a micron levels.
A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric on a conductive layer comprising at least one conductive pattern. Generally, a dielectric barrier or capping layer (also referred to herein as a “diffusion barrier”) is deposited onto the conductive layer prior to deposition of the dielectric. Next, an opening in the dielectric layer is formed by conventional photolithographic and etching techniques, and the opening is filled with a conductive metal, such as tungsten, aluminum, copper, or a copper alloy. Excess conductive material on the surface of the dielectric layer is typically removed by chemical mechanical polishing (CMP). After depositing a diffusion barrier on the metal and exposed surface of the dielectric layer, a second interlayer dielectric is typically deposited onto the barrier.
One such fabrication method is known as damascene and basically involves forming an opening in the interlayer dielectric and filling the opening with a conductive metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive metal, to simultaneously form a conductive plug and electrical contact with a conductive line.
FIG. 1 is a cross-sectional view of a portion 10 of a prior art, conventional semiconductor metal interconnect structure fabricated using damascene processing, wherein trenches (lines) (not shown) and a via (hole) 20 are etched into interlayer dielectric 30, which is disposed atop a semiconductor substrate 15. Conductive metal 50 is deposited into via 20 and planarized. In this embodiment, Ta-based liner 40, made of tantalum, TaN, or TaSiN, is conformally deposited onto sidewalls 21a and 21b and bottom 22 of via 20 (and any trenches, not shown), prior to deposition of metal 50 and planarization. Dielectric barrier 60, traditionally made of SiN, SiC, SiCH, or SiCN, atop metal 50 acts as a diffusion barrier, as well as an etch stop layer. A second dielectric or metal 70 is then deposited atop dielectric barrier 60.
Disadvantageously, however, the atomic transport at the metal/diffusion barrier interface 61 is the most important contributor to electromigration of the metal. Since conductive metals, such as Cu, do not adhere well to the traditional dielectric barrier materials, the interface provides the fastest interfacial diffusion path. Prior solutions to reducing electromigration include using a metallic-based cap (Ta, Pd, or CoWP) for the metal lines, but the increase in the fabrication complexity and in the effective resistivity are undesirable.
Thus, it is known that a diffusion barrier or capping material is needed between the metal and dielectric to reduce the amount of metal diffusion into the neighboring dielectric material. However, because interfacial diffusion at the metal/diffusion barrier interface is the major contributor to reduction in the life-time associated with the electromigration failure in integrated circuits (IC), it is desirable to improve the interfacial bonding at such interfaces to reduce and eliminate the interfacial diffusion. The use of traditional diffusion barriers such as SiN, SiC, SiCH, and SiCN only provide marginal success.
Furthermore, the aforementioned traditional diffusion barriers have dielectric constants larger than 6. It is known, however, that lowering the overall dielectric constants (κ values) of the dielectric layers employed in metal interconnects lowers the resistance capacitance (RC) product of the chip and improves its performance. The high κ values of traditional diffusion barriers increase the overall κ value of the structure and are therefore not acceptable for future high speed ICs.
Thus, a need exists in the semiconductor industry for a diffusion barrier material having improved adhesion to the conductive metal, thereby reducing interfacial metal diffusion. It would also be particularly advantageous if such a material could have a dielectric constant of 3.9 or lower, thereby reducing the overall κ value of the final structure.